发明名称 DATA RECEIVER
摘要 <P>PROBLEM TO BE SOLVED: To provide a data receiver in which the load on a subsequent circuit is reduced and the delay of processing is minimized. <P>SOLUTION: A physical layer circuit receives data over a network and transmits the data via a reception data transmission line. An MAC layer circuit receives the data via the reception data transmission line. The reception data transmission line transmits the data in real time. A load monitoring circuit detects the fact that the load of the data transmitted by the reception data transmission line has exceeded a reference load. A mask circuit masks at least a part of the data being transmitted by the reception data transmission line after the fact that the load has exceeded the reference load is detected by the load monitoring circuit until it is not detected any more. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012195645(A) 申请公布日期 2012.10.11
申请号 JP20110056320 申请日期 2011.03.15
申请人 MURATA MACH LTD 发明人 SURUGA TOMOKI
分类号 H04L29/10;G06F13/00 主分类号 H04L29/10
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