| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which includes a circuit enabling a normal operation without preparing an excessive margin and without changing a design. <P>SOLUTION: A semiconductor integrated circuit 1 comprises: flip flops 10-1 to 10-3; a combined circuit 20 outputting a signal to the flip flop; and a determination circuit 30 outputting a determination signal to the combined circuit. The determination circuit includes a cell delay circuit 32 having a predetermined cell delay amount under predetermined conditions and a wiring delay circuit 34 having a predetermined wiring delay amount under predetermined conditions. The determination circuit generates a determination signal 104 depending on the comparison result between the cell delay amount of the cell delay circuit and the wiring delay amount of the wiring delay circuit. The combined circuit includes one or more delay selection circuits 22-1 to 22-N each including a plurality of logic circuits having the same logic and different delay amounts from one another, and the delay selection circuit selects one from among the plurality of logic circuits based on the determination signal. <P>COPYRIGHT: (C)2013,JPO&INPIT |
