发明名称 |
MEMORY BIT REDUNDANT VIAS |
摘要 |
An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss. |
申请公布号 |
US2012257441(A1) |
申请公布日期 |
2012.10.11 |
申请号 |
US201213528528 |
申请日期 |
2012.06.20 |
申请人 |
DEXTER MARK A.;GUNTURI SARMA S.;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
DEXTER MARK A.;GUNTURI SARMA S. |
分类号 |
G11C29/00;G11C11/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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