TEST STRUCTURE FOR PARALLEL TEST IMPLEMENTED WITH ONE METAL LAYER

摘要

An integrated test circuit includes pads of a padset for testing multiple device under test units (MDUTs). The MDUTs each include devices under test (DUTs). A first integrated test circuit metal layer is patterned to connect the pads to N MDUTs such that a first set of pads are employed for enabling testing of each MDUT and a second set of pads are designated for testing individual DUTs associated with the enabled MDUTs such that N parallel tests may be concurrently performed.