发明名称 |
Memories for electronic systems |
摘要 |
A switch 100 includes a plurality of ports 101 for exchanging data. A shared memory 102 enables the exchange of data between first and second ones of the ports 101 and includes an array 202 of memory cells arranged as a plurality of rows and a single column having width equal to a predetermined word-width and circuitry 202, 204, 206, 208 for writing selected data presented at the first one of the ports 101 to a selected row in the array as a word of the predetermined word-width during a first time period and for reading the selected data from the selected row as a word of the predetermined wordwidth during a second time period for output at a second one of the ports 101.
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申请公布号 |
US8285945(B2) |
申请公布日期 |
2012.10.09 |
申请号 |
US20100751632 |
申请日期 |
2010.03.31 |
申请人 |
RAO G. R. MOHAN;S. AQUA SEMICONDUCTOR, LLC |
发明人 |
RAO G. R. MOHAN |
分类号 |
G06F12/00;G11C7/10;G11C11/408;G11C11/4093;G11C11/4096;H04L12/56 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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