发明名称 Address generator using LUT cascade logic network
摘要 The address generator has a hash network for producing hashed Y1, which is obtained by hushing X1, to an input vector X=(X1, X2), a tentative address generator Y1 for making an address generation function f(X) to a tentative address A′ when no hash collision occurs and otherwise making one of unique addresses A to A′, a data regenerator for producing X″=f−1(A′), a unique address generator for producing A′ when X″ coincides with X and otherwise producing invalid value, a complementary address generator for producing (X) to X, to which the unique address generator produces invalid value, and otherwise producing invalid value, and an output combiner which produces, when the outputs of the unique address generator and the complementary address generator have values other than the invalid value, the values as a unique address A and otherwise produces invalid value as A.
申请公布号 US8285922(B2) 申请公布日期 2012.10.09
申请号 US20070294791 申请日期 2007.03.27
申请人 SASAO TSUTOMU;KYUSHU INSTITUTE OF TECHNOLOGY 发明人 SASAO TSUTOMU
分类号 G06F12/02 主分类号 G06F12/02
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