发明名称 |
Semiconductor memory system including a plurality of semiconductor memory devices |
摘要 |
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. |
申请公布号 |
US8284607(B2) |
申请公布日期 |
2012.10.09 |
申请号 |
US20090645104 |
申请日期 |
2009.12.22 |
申请人 |
SHIBATA NOBORU;SUKEGAWA HIROSHI;KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIBATA NOBORU;SUKEGAWA HIROSHI |
分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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