Gate driving circuit and display device having the gate driving circuit

摘要

An output part outputs a high voltage of a first clock signal as a high voltage of an (m)-th gate signal (m is a natural number) and a low voltage in response to a high signal of an (m+1)-th gate signal outputted from an (m+1)-th stage. A first maintenance part maintains a control part of the pull-up part at a low voltage in response to an (m−1)-th node signal or an (m+1)-th node signal lower than a high signal of a second clock signal having a phase opposite to the phase of the first clock signal received from an (m−1)-th stage or the (m+1)-th stage. A second maintenance part maintains the low voltage of the (m)-th gate signal in response to the (m−1)-th node signal or the (m+1)-th node signal.