| 摘要 |
<P>PROBLEM TO BE SOLVED: To perform timing decision closer to real operation. <P>SOLUTION: The delay calculation/timing verification method includes: a step of holding a net list showing a circuit to be verified; a step of extracting paths between sequential circuits included in the circuit to be verified; a step of calculating timing margins of an input signal with respect to a time for relaxation and constraint that shows a setup time and a hold time set by permitting output of the sequential circuit to be in a meta-stable state; a step of calculating an output delay time when value of the output signal of the sequential circuit is established on the basis of the timing margins; a step of calculating a propagation delay time showing a delay time in a path between the sequential circuits; and a step of verifying timing on the basis of the output delay time, the propagation delay time, and the time for relaxation and constraint. <P>COPYRIGHT: (C)2013,JPO&INPIT |
