发明名称 |
MECHANISMS AND TECHNIQUES FOR PROVIDING CACHE TAGS IN DYNAMIC RANDOM ACCESS MEMORY |
摘要 |
A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.
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申请公布号 |
US2012254700(A1) |
申请公布日期 |
2012.10.04 |
申请号 |
US201113078704 |
申请日期 |
2011.04.01 |
申请人 |
MCGINNIS DARRELL S.;HUDDLESTON C. SCOTT;AGARWAL RAJAT;CHINTHAMANI MEENAKSHISUNDARA R. |
发明人 |
MCGINNIS DARRELL S.;HUDDLESTON C. SCOTT;AGARWAL RAJAT;CHINTHAMANI MEENAKSHISUNDARA R. |
分类号 |
H03M13/05;G06F11/10;G06F12/02 |
主分类号 |
H03M13/05 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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