CHARGE TRAP INSULATOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a technology which improves a maintenance characteristics of a nanoscale charge trap insulator memory unit device and increases a cell integrated capacity by a large number of charge trap insulator cell arrays laminated to the vertical direction with the use of multiple of cell insulator layers.

SOLUTION: The device is composed of: multiple of upper word lines and lower word lines; multiple of bit lines and sensing lines; multiple of memory cell arrays arranged in an intersection region of the upper and lower word lines and bit lines; multiple of memory cells which output storage data from a charge trap insulator to bit lines; a first switching element and a second switching element which selectively and respectively connect the memory cells to bit lines and sensing lines; a P-type float channel whose resistance varies according to a polarity of the charge strap insulator and P-type drain area and P-type source area formed on both sides of the P-type float channel.

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