| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce time required to verify a logic circuit based on a logic simulation. <P>SOLUTION: A logic circuit verification device comprises: a logic simulator for applying a logic simulation to a logic circuit having multiple modules, and for acquiring code coverage (a code covering rate) for each of the modules; and a coverage accelerator for referring to the code coverage for each of the modules, and for instructing the logic simulator to apply the logic simulation to both a module with the code coverage lower than a predetermined rate through the use of a first HDL code and other modules through the use of a second HDL code based on a model with a higher abstraction level than a model to the first HDL code. <P>COPYRIGHT: (C)2013,JPO&INPIT |
