发明名称 ARITHMETIC OPERATION CIRCUIT AND METHOD OF CONVERTING BINARY NUMBER
摘要 An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits.
申请公布号 US2012254271(A1) 申请公布日期 2012.10.04
申请号 US201213410652 申请日期 2012.03.02
申请人 KITAMURA KENICHI;FUJITSU LIMITED 发明人 KITAMURA KENICHI
分类号 G06F7/50;G06F5/01;G06F7/523 主分类号 G06F7/50
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