| 摘要 |
<p>PURPOSE: A digital delay locked loop for timing control in a semiconductor memory is provided to make internal delay proportional to a clock cycle in a low voltage delay by sharing a delay locked loop block in eDRAM macros to reduce PVT variation. CONSTITUTION: A decoder receives a timing code from a delay locked loop. A delay element(106-1 to 106-N) receives the timing code decoded by the decoder and provides a phase delay signal as a response. A phase multiplexer/mixer circuit(120) generates a control signal based on a clock signal and a phase delay signal received from the delay element. A memory array(124) receives a control signal from the phase mixer circuit. [Reference numerals] (108) Phase detection; (112, 118) Thermometer decoder; (120) Phase multiplexer/mixer; (124) DRAM memory array; (AA) Digital DLL; (BB, DD, GG, II) Timing code; (CC) Delay clock; (DD) Timing code; (EE) Timing setting; (FF, HH, JJ) EDRAM macro</p> |
