发明名称 |
Packed restricted floating point representation and logic for conversion to single precision float |
摘要 |
An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures. |
申请公布号 |
US8280936(B2) |
申请公布日期 |
2012.10.02 |
申请号 |
US20060648265 |
申请日期 |
2006.12.29 |
申请人 |
JIANG HONG;INTEL CORPORATION |
发明人 |
JIANG HONG |
分类号 |
G06F7/00;G06F7/38;G06F15/00;H03M7/00 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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