| 发明名称 |
Method and apparatus for performing lutmask based delay modeling |
| 摘要 |
A method for determining a delay through a lookup table (LUT) in a logic array block (LAB) of a field programmable gate array (FPGA) for a signal includes identifying paths through the LUT that are taken for the signal. Delays are computed for the signal only on the paths identified. |
| 申请公布号 |
US8281271(B1) |
申请公布日期 |
2012.10.02 |
| 申请号 |
US20080287828 |
申请日期 |
2008.10.14 |
| 申请人 |
OH JUNGMOO;CARVALHO LYNDON FRANCIS;WYSOCKI CHRIS;ALTERA CORPORATION |
发明人 |
OH JUNGMOO;CARVALHO LYNDON FRANCIS;WYSOCKI CHRIS |
| 分类号 |
G06F9/455;G06F17/50 |
主分类号 |
G06F9/455 |
| 代理机构 |
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代理人 |
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| 主权项 |
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