| 摘要 |
A data processing apparatus including a register bank, a shadow register and an arithmetic operation unit. The register bank includes a number of registers respectively for storing a number of operands wherein the registers are n-bit registers, and n is a nature number. The shadow register stores a first backup operand for making a backup of a first operand, which is stored in a first one of the registers in response to first control signal. The arithmetic operation unit performs at least an arithmetic operation on the operands to obtain operational data, and stores the operational data in the first register in response to an arithmetic operation command. |
