发明名称 |
Memory circuits, systems, and methods for providing bit line equalization voltages |
摘要 |
A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell. |
申请公布号 |
US8279686(B2) |
申请公布日期 |
2012.10.02 |
申请号 |
US20100692512 |
申请日期 |
2010.01.22 |
申请人 |
HSU KUOYUAN PETER;JUNG TAEHYUNG;RYU DOUK HYOUN;KIM YOUNG SUK;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
HSU KUOYUAN PETER;JUNG TAEHYUNG;RYU DOUK HYOUN;KIM YOUNG SUK |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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