| 摘要 |
A packet throttling system is provided for a network head-end device having CPUs and an operating system having interrupt handling code to implement interrupt handlers in one or more of the CPUs for processing interrupts. The packet throttling system comprises a CPU interrupt load examiner, throttling period calculator and interrupt handier terminator. The CPU interrupt load examiner examines, for each of the CPUs, a current CPU interrupt load which is a proportion of a CPU's time that is being spent servicing any interrupt handlers. The throttling period calculator calculates a throttling period for each of the CPUs based on the current CPU interrupt load. The throttling period is a period between permitted packet receptions for the CPU. The interrupt handler terminator terminates a packet reception interrupt handier handling a packet reception interrupt in a receiving CPU if the throttling period of the receiving CPU has not elapsed since the receiving CPU handled a last permitted received packet.
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