发明名称 POWER LINE LAYOUT TECHNIQUES FOR INTEGRATED CIRCUITS HAVING MODULAR CELLS
摘要 An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.
申请公布号 US2012243363(A1) 申请公布日期 2012.09.27
申请号 US201213492469 申请日期 2012.06.08
申请人 LEE CHENG HUNG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 LEE CHENG HUNG
分类号 G11C5/14 主分类号 G11C5/14
代理机构 代理人
主权项
地址