| 摘要 |
An arithmetic processing unit includes a cache memory, a register configured to hold data used for arithmetic processing, a correcting controller configured to detect an error in data retrieved from the register, a cache controller configured to access a cache area of a memory space via the cache memory or a noncache area of the memory space without using the cache memory in response to an instruction executing request for executing a requested instruction, and notify a report indicating that the requested instruction is a memory access instruction for accessing the noncache area, and an instruction executing controller configured to delay execution of other instructions subjected to error detection by the correcting controller while the cache controller executes the memory access instruction for accessing the noncache area when the instruction executing controller receives the notified report.
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