| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a batch fabricated 3D interconnect that decreases consumption at die area and makes the die area utilizable in the interconnection using TWV (Through Wafer Via). <P>SOLUTION: A method of fabricating one or more vertical interconnects is provided. The method includes patterning and stacking a plurality of wafers to form a wafer stack. A plurality of apertures can be formed in the wafer stack within one or more saw streets of the wafer stack, and conductive material can be deposited on sidewalls of the plurality of apertures. The wafer stack can be diced along the one or more saw streets and through the plurality of apertures such that the conductive material on the sidewalls is exposed on an edge portion of resulting stacked dies. <P>COPYRIGHT: (C)2012,JPO&INPIT |
