MEMORY CONTROLLER ADDRESS AND DATA PIN MULTIPLEXING

摘要

PURPOSE: A memory controller address and a data pin multiplexing are provided to share an address and data bits of the maximum pin and to configure a memory controller performing communication with a memory device. CONSTITUTION: A memory controller(102) includes a combination of pins. Each pin is related to data and/or address bit. A programmable logic block(204) is connected to the pins of the memory controller. The programmable logic block uses sub combination in order to transfer data between the memory device and the memory controller according to the size of the memory device. [Reference numerals] (104) 8MB memory device; (106) Latch; (AA) Pindle A16-A31; (BB) Memory controller; (CC) Pindle AD0-AD15; (DD) Programming available logic block; (EE) Free pindle A16-A24; (FF) Address exclusive pindle A25-A31; (GG) A/D pindle AD0-AD15; (HH) SoC; (II) Available for the other application; (JJ) Control signal