| 摘要 |
A shaper of single meander-type pulse packet with programmable width, number and a fixed packet delay relative to a start packet for one cycle comprises two reversible binary counters, first of which is a countdown counter. The counters have a clock input, a counting mode enable input, an asynchronous reset, an overflow output; moreover, the first counter has a synchronous parallel load enable input and a loading input, an inverter, two OR elements, a circuit comprising a resistor and a capacitor, a start-stop device comprising a synchronous D flip-flop having an asynchronous reset, first and second two-input AND elements. A third reversible binary countdown counter is introduced, which has a clock input, a synchronous parallel load enable input and loading inputs, a counting mode enable input, an asynchronous reset, an overflow output, a JK-flip-flop having asynchronous reset; an OR-NOT element, third AND element, AND-NOT element, second, third and fourth inverters. |
