发明名称 |
High speed memory simulation |
摘要 |
In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments. |
申请公布号 |
US8275597(B1) |
申请公布日期 |
2012.09.25 |
申请号 |
US20080020871 |
申请日期 |
2008.01.28 |
申请人 |
OH CHANHEE;CROIX JOHN F.;RATZLAFF CURTIS L.;ACOSTA RAMON D.;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
OH CHANHEE;CROIX JOHN F.;RATZLAFF CURTIS L.;ACOSTA RAMON D. |
分类号 |
G06F17/50;G06F9/54;G06F13/10;G06F13/12;G06G7/54;G06G7/62 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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