发明名称 |
APPARATUS, SYSTEM, AND METHOD FOR TIMING RECOVERY |
摘要 |
Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.
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申请公布号 |
US2012235720(A1) |
申请公布日期 |
2012.09.20 |
申请号 |
US201113048227 |
申请日期 |
2011.03.15 |
申请人 |
JIANG YUEMING;MOHANEVELU RAVINDRAN;ALTMANN MICHAEL W. |
发明人 |
JIANG YUEMING;MOHANEVELU RAVINDRAN;ALTMANN MICHAEL W. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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