| 摘要 |
<p>In this timing error elimination method, a theoretical correction location that can eliminate a timing error of a semiconductor integrated circuit that is to be designed and a first buffer that is inserted into the correction location are selected; regarding the correction location, an empty region on the semiconductor integrated circuit that can dispose the first buffer is searched for; and when there is no empty region, a computer executes a process that searches for a combination that, as the subject of disposing at the semiconductor integrated circuit, is of a plurality of buffers smaller than the first buffer and is able to substitute a delay by means of the insertion of the first buffer.</p> |
