发明名称 CPU OF PLC, SYSTEM PROGRAM FOR PLC, AND RECORDING MEDIUM STORING SYSTEM PROGRAM FOR PLC
摘要 In this invention, a microprocessor controls at least one of a first communication circuit and a second communication circuit such that the following are executed in parallel: a first input/output process including a process that outputs output data from a first transfer buffer to a first instrument of a PLC system bus via the first communication circuit, and a process that inputs input data from the first instrument to the first transfer buffer via the first communication circuit; and a second input/output process including a process that outputs output data from a second transfer buffer to a second instrument of a field network via the second communication circuit, and a process that inputs input data from the second instrument to the second transfer buffer via the second communication circuit.
申请公布号 WO2012124137(A1) 申请公布日期 2012.09.20
申请号 WO2011JP56773 申请日期 2011.03.22
申请人 OMRON CORPORATION;NISHIYAMA, YOSHIHIDE;HAMASAKI, OSAMU;EGUCHI, SHIGEYUKI 发明人 NISHIYAMA, YOSHIHIDE;HAMASAKI, OSAMU;EGUCHI, SHIGEYUKI
分类号 G05B19/05;G06F13/38 主分类号 G05B19/05
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