发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, TEST METHOD AND INFORMATION PROCESSING APPARATUS
摘要 A semiconductor integrated circuit includes a plurality of shift registers to which test patterns are supplied, a pseudorandom number generator configured to generate, based on the test patterns supplied to the shift registers, pseudorandom numbers utilized as masking information corresponding to output responses of the shift registers, a masking information inverter configured to invert, on receiving a first control signal, the masking information corresponding to the output responses of the shift registers indicated by the first control signal, and an initial value storage configured to store initial values of the pseudorandom numbers. In the semiconductor integrated circuit, the pseudorandom numbers generated by the pseudorandom number generator are, on receiving a second control signal, initialized with the initial values of the pseudorandom numbers stored in the initial value storage.
申请公布号 US2012239337(A1) 申请公布日期 2012.09.20
申请号 US201213343015 申请日期 2012.01.04
申请人 MATSUO TATSURU;FUJITSU LIMITED 发明人 MATSUO TATSURU
分类号 G01R31/3177 主分类号 G01R31/3177
代理机构 代理人
主权项
地址