PROVIDING ROW REDUNDANCY TO SOLVE VERTICAL TWIN BIT FAILURES

摘要

PURPOSE: A method and circuit for providing row redundancy to solve vertical twin bit failures are provided to reduce a chip area by including a small register which stores one of row addresses in a failure row. CONSTITUTION: A failure address register(24) stores a first row address and is connected to a first comparator(20). A row address modifier(26) generates a second row address by modifying the first row address received from the failure address register. The first comparator compares the first row address with a third row address. A second comparator(30) compares the second row address with the third row address. [Reference numerals] (AA) 0 row; (BB) 2^n-1 row