| 摘要 |
<p>A configurable memory element for a programmable logic device (PLD) is described comprising an odd latch operable to store an odd data bit and an even latch operable to store an even data bit wherein said odd and even latch are arranged so that an output of the odd latch is chained to an input to the even latch. Control means are provided for configuring the memory element to operate in a first mode in which data can be read from or written to the odd latch and a second mode in which data can be read from or written to the even latch.</p> |
