发明名称 |
Data receiver apparatus and data transmitter apparatus |
摘要 |
Write pointer generation units successively switch and indicate storage locations of data transmitted from a transmitter end LSI from plural buffers constituting FIFO circuits. A clock-step ring buffer delays a gated step signal to instruct an operation stop. When receiving the gated stop signal delayed by the clock-step ring buffer, the write pointer generation units stop switching instructions of the storage locations. |
申请公布号 |
US8271826(B2) |
申请公布日期 |
2012.09.18 |
申请号 |
US20080230115 |
申请日期 |
2008.08.22 |
申请人 |
NAKAGAWA SATOSHI;FUJITSU LIMITED |
发明人 |
NAKAGAWA SATOSHI |
分类号 |
G06F1/00;G06F1/04;G06F9/26;G06F13/00 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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