发明名称 |
Fail safe adaptive voltage/frequency system |
摘要 |
A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.
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申请公布号 |
US8269545(B2) |
申请公布日期 |
2012.09.18 |
申请号 |
US201113285541 |
申请日期 |
2011.10.31 |
申请人 |
CHAWLA NITIN;PARTHASARATHY CHITTOOR;CHATTERJEE KALLOL;KUMAR PROMOD;STMICROELECTRONICS INTERNATIONAL N.V. |
发明人 |
CHAWLA NITIN;PARTHASARATHY CHITTOOR;CHATTERJEE KALLOL;KUMAR PROMOD |
分类号 |
H03H11/26 |
主分类号 |
H03H11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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