发明名称 Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch
摘要 Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The tuning elements are designed to be identical, such that a single design may be used to a signal mismatch that is produced in either direction, using a single design. The tuning elements may be implemented to provide uniformity in the access time through a range of conditions, such as drain voltages and temperatures.
申请公布号 US8271825(B2) 申请公布日期 2012.09.18
申请号 US201113108322 申请日期 2011.05.16
申请人 GOMM TYLER J.;JOHNSON GARY M.;ROUND ROCK RESEARCH, LLC 发明人 GOMM TYLER J.;JOHNSON GARY M.
分类号 G06F1/12;G11C7/10;G11C7/22;G11C11/4076 主分类号 G06F1/12
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