发明名称 |
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures |
摘要 |
The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies. |
申请公布号 |
US8269283(B2) |
申请公布日期 |
2012.09.18 |
申请号 |
US20090653971 |
申请日期 |
2009.12.21 |
申请人 |
CEA STEPHEN M.;GILES MARTIN D.;KUHN KELIN;KAVALIEROS JACK T.;KUHN MARKUS;INTEL CORPORATION |
发明人 |
CEA STEPHEN M.;GILES MARTIN D.;KUHN KELIN;KAVALIEROS JACK T.;KUHN MARKUS |
分类号 |
H01L21/70 |
主分类号 |
H01L21/70 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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