发明名称 Fabrication system of semiconductor integrated circuit, fabrication device, fabrication method, integrated circuit and communication system
摘要 A manufacturing system which can restrain the margin of a semiconductor integrated circuit. The integrated circuit including a fixed circuit unit and a reconfigurable circuit unit outputs, to a configuration determining server, an operation time which was calculated by a detecting unit and a calculating unit. The configuration determining server, by using the operation time obtained from the integrated circuit, calculates performance data which indicates the characteristics of the fixed circuit unit, selects, based on the performance data, a piece of configuration information indicating a circuit configuration that is optimum for the processing of the reconfigurable circuit unit, and outputs the selected piece of configuration information. The integrated circuit builds a circuit in the reconfigurable circuit unit in accordance with the output piece of configuration information.
申请公布号 US8271117(B2) 申请公布日期 2012.09.18
申请号 US20080523834 申请日期 2008.11.14
申请人 ICHINOMIYA TAKAHIRO;HASHIMOTO TAKASHI;PANASONIC CORPORATION 发明人 ICHINOMIYA TAKAHIRO;HASHIMOTO TAKASHI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利