发明名称 Semiconductor integrated circuit with multi-cut via and automated layout method for the same
摘要 A semiconductor integrated circuit includes a first wiring formed on a first wiring layer and prolonged in a first direction, a second wiring formed on a second wiring layer and prolonged in a second direction, a third wiring formed on the first wiring layer and prolonged in the first direction, a fourth wiring formed on the second wiring layer and prolonged in the second direction, a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring. A first overhang is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang, the second overhang being smaller than a third overhang.
申请公布号 US8271926(B2) 申请公布日期 2012.09.18
申请号 US201113137461 申请日期 2011.08.17
申请人 NISHIMUDA KEIICHI;RENESAS ELECTRONICS CORPORATION 发明人 NISHIMUDA KEIICHI
分类号 G06F17/50;H01L23/522 主分类号 G06F17/50
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