发明名称 CLOCK SIGNAL GENERATION CIRCUIT
摘要 A clock signal generation circuit includes a clock inversion unit inverting a reference clock signal and an internal clock signal to generate an inverted reference clock signal and an inverted internal clock signal, a first clock detection unit comparing the reference clock signal with the internal clock signal to output a first detection signal, a second clock detection unit comparing the inverted reference clock signal with the inverted internal clock signal to output a second detection signal, first and second charge pump units generating charge current or discharge current in response to the first second detection signals, respectively, a loop filter unit producing a control voltage signal having a voltage level corresponding to the charge currents or discharge currents, and an internal clock signal output unit producing the internal clock signal according to the control voltage signal.
申请公布号 KR101183626(B1) 申请公布日期 2012.09.17
申请号 KR20100129883 申请日期 2010.12.17
申请人 发明人
分类号 G11C7/22;G11C5/14 主分类号 G11C7/22
代理机构 代理人
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