| 摘要 |
The invention relates to a system-on-a-chip (200, 408) comprising at least one programmable synthesizable core PSC (208, 209) and a dedicated block (201, 202, 203, 207). The PSC core and the dedicated block are synthesized together from a hardware description-language (HDL) model of the dedicated block (201, 202, 203, 207), as well as from a hardware description-language (HDL) model of the PSC core (306, 402) associated with a default configuration file (305, 401). |
