发明名称 ENCODER
摘要 <P>PROBLEM TO BE SOLVED: To provide an encoder capable of reducing a circuit scale and the number of processing cycles. <P>SOLUTION: An encoder 1 includes: a first operation section 33 calculating a first differential value between an input image and a prediction image on a plurality of blocks in a first block size, which are included in a macro block being an encoding object; a second operation section 37 calculating a second differential value between the input image and the prediction image on a plurality of blocks in a second block size larger than the first block size, which are included in the macro block; and a prediction mode determining section 22 determining a prediction mode applied to the macro block based on the plurality of first differential values on the macro block, which are calculated by the first operation section 33, and the plurality of second differential values on the macro bock, which are calculated by the second operation section 37. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012178768(A) 申请公布日期 2012.09.13
申请号 JP20110041270 申请日期 2011.02.28
申请人 MEGA CHIPS CORP 发明人 YASUI MOTOAKI;OKAMOTO AKIRA
分类号 H04N19/50;H04N19/11;H04N19/119;H04N19/134;H04N19/137;H04N19/14;H04N19/176;H04N19/196;H04N19/42;H04N19/593 主分类号 H04N19/50
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