发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT, FAILURE DIAGNOSIS SYSTEM AND FAILURE DIAGNOSIS METHOD |
摘要 |
A semiconductor integrated circuit includes a memory containing multiple memory bits that store predetermined data placed in a first address direction and a second address direction. The semiconductor integrated circuit includes a BIST (Built-in Self-Test) circuit that diagnoses a failure of the memory. The BIST circuit includes a BIST control circuit that controls a BIST on the memory. The BIST circuit includes a failure information table storing: a failed bit-cell position that is an address of a bit cell identified in the first address direction as a failed bit cell by the BIST conducted in the first address direction; the number of bit cell failures at the failed bit-cell position; and a failure overflow flag indicating whether the number of failures exceeds a predetermined upper value or not. The BIST circuit includes a result analyzer that outputs a BIST result obtained by the BIST on the memory. |
申请公布号 |
US2012229155(A1) |
申请公布日期 |
2012.09.13 |
申请号 |
US201113227106 |
申请日期 |
2011.09.07 |
申请人 |
ANZOU KENICHI;TOKUNAGA CHIKAKO;MORISHIMA SHOHEI;KABUSHIKI KAISHA TOSHIBA |
发明人 |
ANZOU KENICHI;TOKUNAGA CHIKAKO;MORISHIMA SHOHEI |
分类号 |
G01R31/3187 |
主分类号 |
G01R31/3187 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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