| 摘要 |
<p>Provided is an integrated circuit, comprising: output units (5, 5a) which are configured to cascade connect a CMOS inverter, configured from first MOS transistors (52, 56) and second MOS transistors (51, 55), which takes a first signal as input and outputs a second signal, with third MOS transistors (53, 54) which receive a control signal which controls the output of the second signal as input into gate terminals and which are in an off state when the control signal denotes that the output of the second signal is suppressed; and fixing units (2, 3, 2a, 3a, 46, 47) which fix the first signal value on the basis of the control signal. When the control signal denotes that the output of the second signal is suppressed, the fixing units (2, 3, 2a, 3a, 46, 47) fix the first signal either to the value whereby the first MOS transistors (52, 56) are in the off state, or to the value whereby the second transistors (51, 55) are in the off state.</p> |
