| 摘要 |
<p>A semiconductor device comprising a substrate (22), a body region (25) adjoining the surface (24) of the substrate (22), a source contact region (26) within the body region (25), a drain contact region (27) adjoining the surface (24) of the substrate (22) and being separated from the body region (25), a dual JFET gate region (33) located between the body region (25) and the drain contact region (27),and a lateral JFET channel region (36) adjoining the surface (24) of the substrate (22) and which is located between the body region (25) and the drain contact region (27), wherein a vertical JFET gate region (32) is arranged essentially enclosed by the body region (25),a vertical JFET channel region (34) being arranged between the vertical JFET gate region (32) essentially enclosed by the body region (25) and said dual JFET gate region (33), a reduced drain resistance region (35) being arranged between said dual JFET gate region (33) and the drain contact region (27), and a buried pocket (23) being located under part of said body region (25), under said dual JFET gate region (33) and under said vertical JFET channel and reduced drain resistance regions (34, 35).</p> |
