发明名称 MULTI-THREADED PROCESSING WITH HARDWARE ACCELERATORS
摘要 Described embodiments process multiple threads of commands in a network processor. One or more tasks are generated corresponding to each received packet, and the tasks are provided to a packet processor module (MPP). A scheduler associates each received task with a command flow. A thread updater writes state data corresponding to the flow to a context memory. The scheduler determines an order of processing of the command flows. When a processing thread of a multi-thread processor is available, the thread updater loads, from the context memory, state data for at least one scheduled flow to one of the multi-thread processors. The multi-thread processor processes a next command of the flow based on the loaded state data. If the processed command requires operation of a co-processor module, the multi-thread processor sends a co-processor request and switches command processing from the first flow to a second flow.
申请公布号 US2012230341(A1) 申请公布日期 2012.09.13
申请号 US201213474114 申请日期 2012.05.17
申请人 MITAL DEEPAK;BURROUGHS WILLIAM;DOSH ERAN;ROSIN EYAL;LSI CORPORATION 发明人 MITAL DEEPAK;BURROUGHS WILLIAM;DOSH ERAN;ROSIN EYAL
分类号 H04L12/56 主分类号 H04L12/56
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