| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technique capable of shortening design TAT while reducing the area of a logic circuit. <P>SOLUTION: A complex logic macro cell is replaced with a basic macro cell, the total sum of the area is extracted, the total sum of the area and the area of the complex logic macro cell are compared, and a complex logic macro cell to be effective for reducing the area is selected. A flag is set to the selected complex logic macro cell. Logic structure retrieval processing of retrieving the equal logic as the macro cell to which the flag is set from logic information is performed, and a flag is set to a basic macro cell to be replacement object. Equivalent logic replacement processing of replacing the basic macro cell to which the flag of the replacement object is set with the complex logic macro cell to which the flag is set is performed. <P>COPYRIGHT: (C)2012,JPO&INPIT |
