发明名称 |
Reducing transistor junction capacitance by recessing drain and source regions |
摘要 |
A semiconductor device, comprising a first transistor having recessed drain and source regions, said drain and source regions are provided in recessed portions of a semiconductor layer and extend to a buried insulating layer; a strained semiconductor alloy provided partially in said drain and source regions, said strained semiconductor alloy inducing a strain in a channel region of said first transistor, wherein a top surface of said strained semiconductor alloy opposite the buried insulating layer is recessed below an interface between a gate insulation layer and the channel region of the first transistor; and an interlayer dielectric material formed above the top surface and in a recessed portion of said strained semiconductor alloy. |
申请公布号 |
EP2428986(A3) |
申请公布日期 |
2012.09.12 |
申请号 |
EP20110192120 |
申请日期 |
2008.06.30 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
FEUDEL, THOMAS;LENSKI, MARKUS;GEHRING, ANDREAS |
分类号 |
H01L21/336;H01L21/265;H01L21/324;H01L21/8238;H01L21/84;H01L27/12;H01L29/417;H01L29/786 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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