发明名称 Layout for high density conductive interconnects
摘要 In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.
申请公布号 US8264010(B2) 申请公布日期 2012.09.11
申请号 US20100830754 申请日期 2010.07.06
申请人 TANG QIANG;GHODSI RAMIN;ROUND ROCK RESEARCH, LLC 发明人 TANG QIANG;GHODSI RAMIN
分类号 H01L27/118 主分类号 H01L27/118
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