发明名称 Erase method and non-volatile semiconductor memory
摘要 An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags, after applying the erase voltage to the at least one of the first and second inner erase units, performing an erase verification on the at least one of the first and second inner erase units, and updating the at least one of the first and second fail flags in accordance with erase verification results.
申请公布号 US8264891(B2) 申请公布日期 2012.09.11
申请号 US20090535903 申请日期 2009.08.05
申请人 KAWAMURA SHOICHI;SAMSUNG ELECTRONICS CO., LTD. 发明人 KAWAMURA SHOICHI
分类号 G11C11/34;G11C16/04 主分类号 G11C11/34
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