发明名称 Phase-locked loop circuit and delay-locked loop circuit
摘要 A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage.
申请公布号 US8264259(B2) 申请公布日期 2012.09.11
申请号 US201113301402 申请日期 2011.11.21
申请人 HIGASHI HIROHITO;FUJITSU SEMICONDUCTOR LIMITED 发明人 HIGASHI HIROHITO
分类号 H03L7/06 主分类号 H03L7/06
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