| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method for executing an addition operation on operands A and B in order to obtain a result R. <P>SOLUTION: The apparatus comprises a prediction circuit for generating a shift indication based on a prediction of the number of leading zeros that would be present in output produced by subjecting the operand A and the operand B to an unlike signed addition. A result pre-normalization circuit performs a shift operation on significands of both operands A and B prior to addition of the significands, and it serves to discard a number of most significant bits of the significands of both operands as determined by the shift indication in order to produce modified significands for the operands A and B. An operand analysis circuit detects, with reference to exponents of the operands A and B, the presence of a leading bit cancellation condition. In the case that the leading bit cancellation condition is present, an addition circuit performs addition of the modified significands for the operands A and B, in order to produce the significand of the result R. <P>COPYRIGHT: (C)2012,JPO&INPIT |
